Qualcomm
Physical Design Engineer (Senior/Lead) - Modem Team
Skills
1 month ago
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Important information
Contract type:
Permanent
Location:
Bengaluru, Karnataka, India
Work mode:
Onsite
Published on:
23 September 2026
What they need
Overview
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
- Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
- PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
Experience
- 2-6 Years of experience in physical design from product-based companies.
Education
- B.E/M.E in ECE, EE, VLSI, Microelectronics, or related fields from a top-tier institute.
Job Summary
Looking for a hands-on Physical Design Engineer with strong expertise in the complete PnR flow, from netlist to GDSII. The candidate will be responsible for block-level implementation, timing closure, and signoff activities for advanced Modem SoC designs.
Key Responsibilities
- Drive end-to-end Physical Design flow including Floorplanning, Placement, CTS, Routing, Timing Closure, and Signoff.
- Perform block-level implementation and optimization for PPA targets.
- Work closely with STA, RTL, DFT, and CAD teams to achieve design closure.
- Debug and resolve implementation issues using Synopsys Fusion Compiler.
- Develop automation and flow improvements using Tcl/Shell scripting.
Required Skills
- Strong hands-on experience in Floorplanning, Placement, CTS, Routing, Timing Closure, and Signoff.
- Expertise in Synopsys Fusion Compiler (FC)/Innovus and implementation flows.
- Proficiency in Tcl and Shell Scripting
- Good understanding of STA, MMMC, IR/EM, DRC/LVS, and Physical Verification.
- Must have practical block-level implementation experience with strong command-level knowledge of FC/Innovus tools.
- Experience with advanced technology nodes and full-chip/tapeout environments.
- Strong debugging, problem-solving, and communication skills.
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