Principal Engineer, Dft

Job Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Role Overview

Qualcomm's Global CAD Organization is seeking a highly experienced and innovative technical leader to drive the development and deployment of next-generation DFT, ATPG, and MBIST methodologies for industry-leading SoCs built on advanced semiconductor technology nodes. In this strategic role, you will work within a highly collaborative global environment, partnering with SoC Design, DFT, Product Engineering, Test Engineering, Diagnostics teams, and leading EDA vendors to define and deliver scalable, high-quality Design-for-Test solutions that enable first-pass silicon success and manufacturing excellence.

This position offers a unique opportunity to influence company-wide DFT methodology direction, drive technology innovation, and contribute to the development of cutting-edge mobile, AI, automotive, and compute products.

Key Responsibilities

• Lead the architecture, development, integration, and deployment of advanced DFT, ATPG, MBIST methodologies and flows across the complete product lifecycle, from RTL design through post-silicon validation and production test.
• Collaborate closely with global DFT teams and EDA partners to develop scalable and efficient solutions that improve productivity, quality, and test coverage.
• Evaluate emerging DFT technologies, tools, and methodologies through proof-of-concepts, methodology studies, design-of-experiments (DoE), and joint development initiatives with EDA vendors.
• Drive methodology enhancements, automation frameworks focused on improve design productivity, minimizing test cost and test time, and maximizing defect coverage and silicon quality.
• Define and execute the DFT methodology roadmap to address future product requirements, technology scaling challenges, and evolving test strategies.
• Provide technical leadership, mentorship, and guidance to engineering teams while influencing cross-functional stakeholders and driving alignment across global organizations.

Qualifications

• Bachelor's, Master's, or higher degrees in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• 12-15 years of industry experience in VLSI CAD/EDA methodology development with significant focus on DFT, ATPG, and test optimization methodologies.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

Required Technical Skills

• Deep expertise in DFT methodologies, including:
  • Scan insertion and optimization
  • ATPG development and test compression
  • Memory BIST (MBIST)
  • Fault modeling and coverage analysis
• Strong hands-on experience with industry-standard DFT, ATPG, MBIST tools such as: Siemens Tessent, Synopsys TestMAX, SMS
• Proven track record of driving methodology innovation and delivering measurable improvements in test quality, productivity, and execution efficiency.
• Strong programming and automation skills using TCL, Python
• Solid understanding of SoC DFT architecture, Product test engineering practices, ATE environments, silicon bring-up, and manufacturing test flows.
• Experience working with software development best practices including version control, configuration management, release processes, quality assurance, and support infrastructure.
• Demonstrated ability to lead complex technical projects, influence cross-functional teams, and drive successful execution in a global engineering environment.
• Exposure to development of AI/ML-based solutions, and intelligent automation to enhance DFT implementation workflows.

Preferred Leadership Attributes

• Strong technical leadership with the ability to define vision, influence strategy, and drive execution.
• Excellent communication, presentation, and stakeholder management skills.
• Ability to collaborate effectively across geographically distributed teams and diverse functional organizations.
• Self-driven, highly organized professional with strong analytical problem-solving capabilities.
• Passion for technology innovation and continuous improvement.

Keywords

Keywords: DFT, ATPG, Scan Insertion, Scan Compression, MBIST, Tessent, TestMAX, TetraMAX, VLSI Test, DFT CAD Methodology, SoC DFT, DFT EDA Tools, Semiconductor Test and Diagnostic