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Senior Lead Physical Design Engineer-Cpu

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Onsite

Senior Lead Physical Design Engineer-Cpu

Qualcomm

Senior Lead Physical Design Engineer-Cpu

Skills

Node

2 months ago

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Important information


Contract type:

Permanent

Location:

Noida, Uttar Pradesh, India

Work mode:

Onsite

Published on:

25 August 2026

What they need


Job Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
  • OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
  • OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Responsibilities

  • Qualcomm Noida CPU team is hiring for developing high performance and power optimized custom CPU cores. Individuals to Handle hardening complex HMs from RTL to GDS [ Synthesis, PNR, Timing ].

Desired Experience

  • 5+ years of experience in Physical design, STA in CPU Domain.
  • Solid understanding of industry-standard tools for physical implementation: Genus, Innovus, FC, PT, Tempus, Voltas, and redhawk.
  • Solid grip from floorplan to PRO and timing signoff along with understanding of IR drop and physical verification aspect.
  • Experience in preparing complex ECOs for timing convergence across a huge set of corners through Tweaker, Tempus, and Physical PT ECOs.
  • Should be aware about the tricks for minimizing power.
  • Experience in deep submicron process technology nodes is strongly preferred.
  • Knowledge of high performance and low power implementation methods is preferred.
  • Willing to push PPA to the best possible extent.
  • Strong fundamentals.
  • Expertise in Perl, TCL language

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