Soc Power Architecture Engineer

Company: Qualcomm India Private Limited

Job Area: Engineering Group, Hardware Engineering

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Description

Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs.

Skills/Experience

• At least 3-5 years of experience are required in the following areas:
• Strong Design concepts, especially understanding of SoC boot up, Power Domain crossings, Cross corner timing
• Low power intent concepts and languages (UPF or CPF)
• Power dissipation and power savings techniques
• Dynamic clock and voltage scaling
• Power analysis (leakage and dynamic) and thermal impacts
• ASIC Power grids and PCB Power Distribution Networks
• Outstanding written and verbal communication skills

Additional skills in the following areas are a plus:

• Power estimation and reduction tools (PowerArtist/PTPX, Calypto)
• Mobile Baseband application processors chipset and power grid understanding
• UPF-based synthesis and implementation using Design Compiler
• Structural low power verification tools like CLP or MVRC
• Power Software features for power optimization
• Voltage regulators including Buck and Low Drop out
• Experience in leading/mentoring a small to medium size engineers is an added plus

Responsibilities

• Defining chip and macro level power domains
• System Level Power Modeling
• Mixed signal power analysis
• Power Island/Power Gating/Power Isolation
• Structural Low power design of level shifter and isolation cell topology and associated rules
• Architectural analysis and development of digital power optimization logic/circuits/SW
• Work with Power Management IC developers for power grid planning
• Creating detailed architecture and implementation documents

Education Requirements

• Required: Bachelor's, Computer Engineering and/or Electrical Engineering
• Preferred: Master's, Computer Engineering and/or Electrical Engineering