PTPX Power/PNR Engineer

MTS Silicon Design Engineer - PTPX Power Engineer

Job Summary

Responsible for power analysis, power optimization, and signoff of complex SoC/IP designs using PrimeTime PX (PTPX) and related power methodologies. The engineer will drive dynamic and leakage power convergence, identify power bottlenecks, develop power reduction strategies, and collaborate across PD, RTL, Architecture, Timing, DFT, and Power teams to achieve product power targets.

Key Responsibilities

• Perform block, tile, and full-chip power analysis using PrimeTime PX (PTPX).
• Analyze dynamic, leakage, clock, memory, and switching power components to identify optimization opportunities.
• Drive power convergence across project milestones and signoff stages.
• Correlate power across RTL, synthesis, implementation, and silicon projections.
• Debug high-power hotspots and recommend architecture, RTL, clocking, and physical design optimizations.
• Execute power regression flows and generate power dashboards, reports, and trend analysis.
• Collaborate with PD, timing, clocking, and RTL teams to implement power-reduction solutions.
• Develop automation, scripts, and methodologies to improve power analysis efficiency and accuracy.
• Support power signoff reviews and customer-facing power deliverables.

Required Qualifications

• Bachelors or Masters degree in Electrical Engineering, Electronics Engineering, VLSI, Computer Engineering, or related field.
• 7 to 10 years of experience in ASIC Physical Design, STA, or Power Analysis.
• Strong understanding of digital design, CMOS power fundamentals, and low-power design techniques.
• Hands-on experience with PrimeTime PX (PTPX) or equivalent power analysis tools.
• Good understanding of activity propagation, SAIF/VCD-based power analysis, and switching activity estimation.
• Familiarity with synthesis, STA, clocking, and physical design flows.
• Proficiency in Tcl, Python, Perl, or Shell scripting.
• Strong analytical, debugging, and problem-solving skills.

Preferred Experience

• Experience in SoC power signoff for CPU, GPU, AI/ML, networking, or datacenter products.
• Strong understanding of clock power optimization, power gating, multi-Vt strategies, DVFS, and low-power methodologies.
• Experience correlating RTL power, implementation power, and silicon power measurements.
• Exposure to advanced process nodes (5nm, 4nm, 3nm, or below).
• Experience with PrimeTime, Fusion Compiler, RedHawk, Joules, PowerArtist, or similar EDA tools.
• Knowledge of UPF/CPF, IR/EM considerations, and thermal-aware power analysis.
• Ability to independently drive power closure for critical blocks and mentor junior engineers.
• Experience developing power automation flows, dashboards, and AI-assisted power optimization methodologies.

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