Senior Verification Engineer-WIOT

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Description About the Business Unit Ceva is at the forefront of the Smart Edge revolution, with innovative state-of-the-art Silicon and Software solutions that enable products to Connect, Sense and Infer.

Within the Wireless Internet of Things (WIoT) Business Unit, we are offering you a unique opportunity to shape the future of connected devices. Our advanced wireless technologies, including Bluetooth, Wi-Fi, UWB and 5G Cellular IoT, are integrated into over a billion devices annually, driving innovation across industries.

About The Role We are looking for an experienced Senior Verification Engineer to join our WIOT verification team.

The role involves verification of complex Bluetooth, Bluetooth Low Energy (BLE) and IEEE 802.15.4 features at IP and subsystem level, with a strong focus on protocol behavior, integration and end-to-end verification.

We are looking for a highly autonomous engineer with strong technical ownership, capable of working independently while collaborating effectively with verification engineers, RTL designers, architects and cross-functional teams.

Responsibilities **** Develop and maintain SystemVerilog/UVM verification environments from scratch, including constrained-random tests, reusable UVM components, assertions and functional coverage

Integrate multiple verification environments and verification IPs into larger subsystem and system-level environments

Define verification plans and test scenarios, and verify Bluetooth/BLE and IEEE 802.15.4 features, protocol behavior, corner cases and error conditions

Debug complex RTL and testbench issues and drive verification activities from planning and environment development through coverage closure

Drive technical topics autonomously with limited supervision while collaborating closely with verification engineers, RTL designers, architects and other cross-functional teams

Support the integration team (Links = Bluetooth + Wi-Fi) with the integration of the Bluetooth verification environment into larger connectivity environments

Requirements

• 7+ years of ASIC/SoC verification experience
• Strong SystemVerilog, UVM and SystemVerilog Assertions (SVA) knowledge, with proven experience building UVM verification environments from scratch
• Experience integrating multiple verification environments, with a good understanding of RTL and digital design
• Strong debugging and problem-solving skills
• High level of autonomy, technical ownership, collaboration and communication skills across teams and departments
• Fluent English

Advantages ****

• Knowledge of Bluetooth / Bluetooth Low Energy (BLE) and IEEE 802.15.4 standards
• Wireless protocol and IP verification experience, including subsystem or SoC-level verification
• Python or other scripting language experience
• Formal verification experience