ASIC RTL Design Engineer

Job highlights

• B Tech / M Tech in Microelectronics,Electrical Engineering or Computer Science
• QUALIFICATION: 4-12+ YEARS EXPERIENCE
• Hands on industry experience in RTL development .
• Experience with Verilog or System-Verilog in complex IP and SOC design .
• Experience with linting tools,CDC and formal verification . .

QUALIFICATION: 4-12+ YEARS EXPERIENCE
B. Tech/M. Tech in Microelectronics, Electrical Engineering or Computer Science. Other Science graduates would be considered if they have relevant experience

REQUIREMENTS

• Hiring for Senior Engineer, Technical Lead, and Architect levels

• Hands on industry experience in RTL development

• Experience with Verilog or System-Verilog in complex IP and SOC design

• Experience with linting tools, CDC and formal verification

• Proven track record of delivering high quality designs

• Block level and system level verification experience using bus functional models and/or verification IP

• Mentor, Cadence or Synopsys simulation tools

• Proven ability to work in a small company environment

RESPONSIBILITIES

• Contribute to the design and development of the next generation of IP products

• Develop innovative micro-architectures

• Deliver high-quality RTL code using System Verilog

• Work with customers to successfully integrate our products into their designs.