EMIR / Power Integrity Engineer

Jb details

Engineering / Physical Design

India

Full-time

Hybrid

We are seeking a skilled EMIR / Pwer Integrity Engineer t jin ur SC Physical Design team. The ideal candidate will be respnsible fr pwer delivery netwrk (PDN) planning, pwer integrity analysis, EMIR verificatin, and signff fr advanced semicnductr designs. The rle invlves ensuring reliable pwer delivery acrss the chip thrugh static and dynamic IR drp analysis, electrmigratin verificatin, pwer grid ptimizatin, and ECO implementatin t achieve signff-quality designs.

Key Respnsibilities

• Perfrm Pwer Integrity and EMIR analysis fr cmplex SC, subsystem, and IP designs.
• Develp, analyze, and ptimize Pwer Delivery Netwrks (PDN) t meet perfrmance, pwer, and reliability requirements.
• Execute Static IR Drp, Dynamic IR Drp, and Electrmigratin (EM) analysis thrughut the design cycle.
• Define simulatin methdlgies, run setups, and signff criteria fr pwer integrity verificatin.
• Develp and enhance CAD-based EMIR analysis flws incrprating timing, package, and bard-level abstractins.
• Identify, debug, and rt-cause EM, Static IR, and Dynamic IR vilatins.
• Prvide and implement ECO slutins t reslve pwer integrity vilatins, including pwer grid enhancements, strap ptimizatin, cell spreading, decap insertin, pwer ruting imprvements, and layut mdificatins.
• Validate ECO effectiveness thrugh iterative EMIR analysis and drive cmplete signff clsure.
• Cllabrate clsely with Physical Design, CAD, RTL, Package, and Reliability teams t achieve pwer integrity gals.
• Autmate analysis, debugging, and reprting flws using Tcl, Pythn, Perl, r Shell scripting.
• Supprt advanced technlgy ndes and cntribute t methdlgy develpment and cntinuus imprvement.

Required / Preferred Qualificatins

• Bachelr's r Master's degree in Electrical/Electrnics Engineering r related field.

• 5+ years f ASIC/SC EMIR experience.

• Knwledge f UPF and lw-pwer design methdlgies.

• Experience develping signff methdlgies and CAD autmatin flws.

• Understanding f package parasitics and pwer delivery architecture.

• Strng analytical, debugging, and cmmunicatin skills.

• Strng understanding f:

  • Pwer Delivery Netwrks (PDN)
  • Electrmigratin (EM)
  • Static and Dynamic IR Drp Analysis
  • Pwer Integrity and Reliability Cncepts
  • CMOS Fundamentals

• Familiarity with Physical Design flw including Flrplanning, Placement, CTS, Ruting, and Signff.

• Experience with advanced technlgy ndes (7nm, 5nm, 3nm, r belw).

• Strng scripting skills in Tcl, Pythn, Perl, r Shell.

Tls Required

• Cadence Vltus, Ansys RedHawk/RedHawk-SC, Synpsys PrimeRail/PrimePwer fr EMIR, Static/Dynamic IR Drp analysis, Pwer Integrity verificatin, and signff.
• Cadence Innvus / Synpsys ICC2 / FC_SHELL fr pwer grid implementatin, ECO executin, decap insertin, and EMIR clsure.
• Tcl, Pythn, Perl, and Shell Scripting fr flw autmatin, methdlgy develpment, debugging, and reprting.