芯联集成电路(上海)有限公司
设计工程师1(J10950)
2 months ago
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Important information
Contract type:
Permanent
Location:
Shanghai, China
Work mode:
Onsite
Published on:
23 August 2026
What they need
该职位来源于猎聘 职责描述： 1.负责数字IP微架构和电路设计或子系统/系统集成设计工作 2.负责设计规格和其它相关文档编写，数字设计流程检查，自测，预综合等 3.参与IP架构和规格讨论与制定 4.协助验证工程师进行设计相关问题定位及覆盖率收集 5.协助中后端及DFT工程师解决相关设计问题 6.负责FPGA集成设计工作，协助FPGA验证工程师定位相关设计问题 7.协助测试工程师进行样片和量产测试问题调试定位 8.参与流程建设和维护，参与设计方法学完善和开发 任职要求： 1.硕士及以上学历，微电子，集成电路等相关专业 2.掌握数字IC前端设计流程和常用前端EDA工具 3.精通Verilog HDL语言，熟悉System Verilog/C/C++语言以及脚本语言等 4.了解ISO26262标准经验者优先 5.积极主动，沟通顺畅，责任感强，自学能力强，有良好的团队合作精神
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