豪威集团
CD001-数字电路设计工程师(J11836)
2 months ago
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Important information
Contract type:
Permanent
Location:
Chengdu, Sichuan, China
Work mode:
Onsite
Published on:
14 August 2026
What they need
该职位来源于猎聘 职责描述： 1.负责模块设计，撰写文档 2.负责制定模块验证计划、仿真及分析验证覆盖率
- 负责synthesis等design flow方面的工作
- 负责模块的FPGA原型验证 任职要求： 1.熟悉计算机体系结构，熟悉ASIC设计流程 2.熟练掌握Verilog硬件设计语言、RTL设计方法学，熟练使用各种常用的仿真工具
- 理解逻辑综合、时序分析、形式验证等基本概念 4.熟练掌握C/C++语言，能使用C语言对硬件建模，协同硬件仿真
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