苏州盛科通信股份有限公司
芯片设计工程师(南京)
Skills
il y a 1 an
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Important information
Contract type:
Permanent
Work mode:
Onsite
Published on:
12 août 2026
What they need
该职位来源于猎聘 工作职责: 1. 根据规格书,撰写模块或者子系统的设计方案及文档; 2. 完成模块的RTL编码和IP集成设计,对模块做综合、时序优化; 3. 根据后端反馈改进模块设计和代码; 4. 支持负责模块的验证和硬件调试。 任职要求: 1. 熟悉Verilog、Systemverilog、C语言等; 2. 熟悉VCS、VERDI、DVE等EDA仿真及调试工具; 3. 理工科专业毕业,有较强的解决问题的逻辑思路和方法论; 4. 具备快速学习能力和较强的沟通交流能力,能够熟练阅读英文专业文档; 5. 具备较强的抗压能力; 6. 有相关项目经验或实习经验者优先。
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