数字IC整合工程师

该职位来源于猎聘 Job Description

• Responsible for SOC chip-level and sub-system level integration task.
• SOC/sub-system hierarchical architecture plan, RTL design rule check, RTL synthesis, equivalent check, timing sign-off, timing ECO, low power design rule check, performance/power/area quality boost, and etc.
• Support chip-level/sub-system physical implementation, including floorplan, power plan, placememt, clock tree synthesis, routing, LVS/DRC, and etc. Job requirements:
• MSEE degree or above in microelectronics, computer, electronic engineering, communication engineering, and other related fields.
• Familiar with Verilog and ASIC front-end design flow, with solid digital circuit theory foundation, hands-on ability and innovation ability.
• Professional in IC EDA tools(such as Spyglass/Genus/DC/PT/LEC/CLP/DFTC/TestMax/Tessent/Innovus/ICC and etc), and with ASIC design experience, such as RTL coding, Synthesis, P&R, STA timing sign-off, IR Analysis Post-silicon diagnosis and etc.
• Familar with scripting language, such as Makefile/Tcl/Perl/Python, and etc.
• Good communication and team-work skills, good English communication and presentation experience.
• Passion work attitude, full of curiosity about technology, courage to take responsibility, and able to work under strong pressure. Work location: 合肥Hefei (MHF site)