杭州集睿科技有限公司
IC 设计工程师
Skills
PythonGit
2 months ago
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Important information
Contract type:
Permanent
Work mode:
Onsite
Published on:
12 August 2026
What they need
该职位来源于猎聘 岗位职责: 1. 负责ASIC模块级设计开发; 2. 参与或负责ASIC芯片级设计开发; 3. 编写硬件驱动程序与文档; 4. 协同调试FPGA原型; 5. 协同调试ASIC芯片。 任职要求:
- 相关工作经验 3 年以上,本科及以上学历;
- 熟悉下列协议或数据处理方法中的若干项:
RISCV CPU 系统,AMBA 总线,DDR 接口;
视频接口如HDMI,DP,MIPI,LVDS;
USB Type-C, USB2.0, USB3.x, USB4;
- 熟悉 Verilog,SystemVerilog语言;VCS, VERDI仿真及调试工具;
- 熟悉 C 语言和 RTOS 程序开发及调试;python, tcl 脚本编写;
- 具有良好的沟通能力和团队合作能力;
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