數位IC驗證資深工程師/專案副理

Location : 新竹科學園區

Work experience : 3 year

Education : 碩士

工作項目：

Verification for a CPU design project, which includes:

• Responsibility for test plans, testbench documentation and implementation.
• Use SystemVerilog language, SVA and UVM methodology for block and top level verification.
• Apply formal property checking/formal verification methodologies
• Understanding of the fundamentals of computer architecture

應徵條件：

1. 碩士以上；電機、電機與控制、資訊工程、電子相關科系畢業為主。

2. 具相關工作經驗者尤佳。