瑞昱半導體股份有限公司
IC Layout工程師
8 months ago
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Important information
Location:
Taiwan
Work mode:
Onsite
Published on:
25 September 2026
What they need
Location : 新竹科學園區
Work experience : 0 year
Education : 大學
工作項目：
IC Fully Layout.
應徵條件：
大學以上; 電機、電機與控制、電子等相關科系畢業為主。
需會操作 Virtuoso XL/Mentor Calibre verification/Totem。
具備 Fin-FET先進製程及 ESD、latch up、IR/EM相關知識。
具 Mixed mode佈局相關經驗者尤佳。
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