纷美包装
数字前端设计工程师（ISP方向）
Skills
9 months ago
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Important information
Contract type:
Permanent
Location:
Shanghai, China
Work mode:
Onsite
Published on:
17 August 2026
What they need
该职位来源于猎聘 岗位要求： 1.熟练掌握Verilog HDL，能够使用RTL描述复杂数字电路 2.熟悉VCS/Verdi等常见debug工具，能够对大规模数字电路进行仿真及debug 3.能够采用Design compiler(或Quartus/Vivado/Synplify等FPGA工具)对RTL设计进行综合并分析时序、面积 4.熟悉DDR读写原理，熟悉常见片上总线规范（例如AMBA AXI） 5.对数字图像信号处理（ISP）、图像降噪、图像画质增强等机器视觉相关方向有强烈的学习意愿 岗位关键字： 数字前端设计，ASIC前端设计，RTL设计、ISP，图像降噪、图像画质增强
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