David Levy

Architecture exploration and multiple implementations of the SHA-256 for Bitcoin mining.

Development of the VESA DSC standard for image compression over HDMI and Display Port. Architecture modifications for timing improvements. Add new features as support for 4:2:2 and 4:2:0 modes. Complete design and verification in Verilog. Synthesis for FPGA on Quartus

I wrote all Verilog code for all the blocks and DSP extensions mentioned below. I mentored 2 students to help with verification. I defined the verification plan for all blocks and wrote all specifications. Channel State Information for LTE: ● HW architecture of configurable Neural Network for Mean MIB function approximation ● HW architecture of DSP extensions: - QR matrix decomposition - Log2 approximation - Binary Search Internet of Things for LTE (Category M): ● HW/SW partitioning for Viterbi decoder, Turbo code encoder and uplink rate matching ● SW architecture for uplink rate matching ● HW architecture of DSP extensions for - AES ciphering - Viterbi ACS and Traceback - Turbo code interleaver and convolutional encoder - Rate matching basic functions: shuffle, transpose and permute

Architecture and micro-architecture specification, HW/FW partitioning of a Magnetic Sensor digital part. Architecture specification, HW/FW partitioning of combined PSI5 and DSI3 receivers. Matlab models of threshold adaptation algorithm and symbol decoding algorithm based on correlation. Architecture specification, HW/FW partitioning of an event verification controller IP in an Airbag controller chip. Coordinator between the different team members: digital and analog designers, verification and test engineers, project manager and functional safety engineer. Development following the ISO26262 process for a HW component.

WiFi IP architecture specification for 3 product generations. Responsible for converting the 802.11n standard features to HW PHY and MAC requirements. Features specification improving both power and reach of the WiFi IP involving both HW and FW. WiFi Alliance member and contributor.

ASIC team leader (5 designers): ADSL chip improvement. DSP: Viterbi decoder & error correction decoder algorithm analysis with C models, improvement, implementation in VHDL and synthesis. FFT implementations comparison with C models. System architecture specification and design follow-up of an ADSL TC IP with an embedded ARM7.

VHDL Design, testing, integration and synthesis of ADSL and ATM functional units for an ADSL digital chip with two embedded DSP’s.