Hadeer Khaled

The training gives expertise in analog circuit analysis, design, and verification, along with advanced analog building blocks and RF circuits. Topics include differential amplifiers, and op-amps design flow by utilizing standard design and testing steps for schematic and layout. Moreover, students explore the process of design analog circuits and different filters. Also, the impedance matching, signal propagation, transmission lines, noise analysis and minimization as well as the behavior of RF circuits at different frequencies. One of the goals is to enhance the capability of the design and integration of modern RF circuits blocks including LNAs, mixers, antennae, filters, voltage-controlled oscillators, etc. The advanced analog building blocks cover three main topics: data converters, timing circuits (PLLs), and power management. The topics include ADC/DAC, Switched Capacitor Circuits, SAR ADC: CDAC & Comparators, Pipelined ADC, Sigma delta modulators, DACs, PLL fundamentals and circuits, DLLs, Power Management ICs, bandgap reference circuits, linear regulators and LDOs, switched-capacitor power converters, industrial issues, and battery chargers. These modules are delivered by worldwide industry experts and university professors. Through hands-on experience in the labs with industry-standard CAD tools, the trainee successfully completes assignments and projects for each course. The CAD tools include: Cadence Virtuoso, Spectre, EMX, CST, and Suitera, Siemens's flow (Tanner EDA: S-Edit, L-Edit, W-Edit, Calibre), Questa, and Intel's Quartus. Languages: Verilog

The training gives expertise in digital design flow for ASIC including Verilog modelling, synthesis, minimization, standard-cell libraries, timing optimization, timing models, timing analysis & constraints, Clock Tree Synthesis, placement and routing, Signoff and chip finishing, and design for testing. Regarding the verification and testing of digital systems, the SystemVerilog concepts such as Data types, Function, threads, Interfaces, randomization, Code Coverage, Functional Coverage and Assertion Based Verification are covered. In addition to OOP and Hierarchal Testbenchs. UVM verification projects including components such as transaction, generator, configuration, sequencer, driver, monitor, also, faults in digital systems, test generation and testable systems, and pattern generation and comparator circuits of the built-in-self-test. In addition, the VLSI and full custom IC design flow topics learned include design of complex digital circuits, PLA, Arithmetic Blocks, Memory Design, system interconnect, Clock Generators and System Level Integration and it is emphasizing principles such as power optimization, timing analysis, and signal and power integrity issues. These modules are delivered by worldwide industry experts and university professors. Through hands-on experience in the labs with industry-standard CAD tools, the trainee successfully completes assignments and projects for each course. CAD tools include: Synopsys's flow (Design Compiler, Formality, Library Manager, ICC2, PrimeTime, VCS, Verdi), Siemens's flow (Tanner EDA: S-Edit, L-Edit, W-Edit, Calibre), Questa, Intel's Quartus, and Cadence Virtuoso. Languages: SystemVerilog, Verilog