Jitendra Manjunath Gowda

Intro

I'm a Physical Design and Analog Layout Engineer with a passion for getting the details right — whether that's routing symmetry in an analog block or timing closure in a complex ASIC flow. I'm currently wrapping up my Master of Engineering in Electrical and Microsystems at OTH Regensburg, with my thesis completed at IMMS Erfurt on layout strategies for CDAC arrays in SAR ADCs. The work involved designing and comparing multiple analog layout topologies, running post-layout PEX simulations, and evaluating ADC performance using Cadence Virtuoso — the kind of hands-on analog work I genuinely enjoy. Before my Master's, I worked as a Physical Design Engineer at SOCDV Technologies, where I was part of a 28nm ASIC project — 52k standard cells, 40 macros, 9 metal layers — handling everything from floorplanning and placement to CTS, routing, and ECO-based timing closure using Synopsys ICC2. What I work with: Analog Layout — common-centroid, interdigitation, shielding, parasitic-aware routing ASIC Physical Design — floorplanning, CTS, routing, timing closure, DRC/LVS, PEX Tools: Cadence Virtuoso, Synopsys ICC2, Assura DRC/LVS, KiCAD Programming: C, C++, Python, TCL | Linux environments My main focus is Analog Layout, Physical Design, and Custom IC/ASIC roles — but I'm also genuinely open to broader electronics and hardware engineering opportunities where my background can be useful. Outside of work I enjoy badminton, travelling, and sports — and I'm actively working on improving my German beyond A2! 📍 Regensburg, Germany | Open to relocation across Germany and EU 🕐 Part-time now (20 hrs/week) | Full-time from July 2026 🌐 English (C1) | German (A2) | Kannada (Native) | Hindi (Proficient)

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