Mauro L. de Freitas

https://lituus.fr/

The power-domain non-orthogonal multiple access (NOMA) schemes can outperform conventional orthogonal multiple access (OMA) schemes in cellular networks. However, when leading with Massive MIMO systems, the base stations have many more antennas than there are users in the cell and, as a consequence, more research is need in NOMA to efficiently communicate in this setup. keywords: 5G, NOMA, matlab, detection, equalization, Massive MIMO, beamforming.

PhD Student at Université de Lille 1, Institut de Recherche sur les Composants logiciels et matériels pour l'information et la Communication Avancée (IRCICA) - USR CNRS/Lille 1 n°3380 and Institut d’Electronique et de Microélectronique et de Nanotechnologie (IEMN) - UMR 8520 Lille 1. My research interests encompass impulsive noises, radio channel, interference modeling, alpha-stable distributions (non-Gaussian processes) and the study on the choice of appropriate noise model which is no longer gaussian as traditional research. keywords: 5G, IoT, M2M, interference, noise, non-gaussian models

Courses: - Random signals; - VHDL numeric systems.

ESBMC is a context-bounded model checker for embedded C/C++ software based on Satisfiability Modulo Theories (SMT) solver. It allows the verification engineer to verify single- and multi-threaded software (with shared variables and locks); to reason about arithmetic under- and overflow, pointer safety, memory leaks, array bounds, atomicity and order violations, deadlock and data race; to verify programs that make use of bit-level, pointers, structs, unions and fixed-point arithmetic. More information: http://www.esbmc.org/ and http://dsverifier.org/ keywords: model checking, satisfiability, git, fixed point, ESBMC

- ASIC Project (Frontend Design and Verification) - Digital IC Designer (Verilog and VHDL): System architecture definition, Python modeling, RTL architecture definition, specification document development, RTL coding, HDL analysis (HAL tool), functional simulation (NCsim, ModelSim). - Verification using SystemC and SystemVerilog. - Experience with Redmine and MS Project. - Digital IC Silicon Evaluation Environment Developer: Silicon evaluation environment architecture definition, planning, implementation and debugging. FPGA (Altera/Xilinx), Python. - FPGA prototyping: Altera/Xilinx, Verilog/VHDL. - Keywords: ASIC, VLSI.

Programmer in Sistoque and SisCommerce Systems. • Software for stock control and inventory. • Invoice system. • Creation of the automatic backup system.