Sami Lazreg

Software architecture, hands-on development and technical leadership in R&D, spanning software verification and MBSE engineering toolchains. C/C++ VERIFICATION ENGINE MODERNISATION A tightly coupled legacy C engine made new verification capabilities costly to implement and risky to integrate. • Designed and implemented an incremental migration to modular C++20, introducing strong types, RAII, explicit ownership and reusable APIs. • Decoupled verification algorithms from model representations through generic programming and configurable exploration policies. • Delivered a shared core supporting 3 migrated and 2 new verification families, with regression and differential testing against the legacy engine and integration tests in CI.

CUBESAT DESIGN AND SIMULATION TOOLCHAIN Early-stage design lacked an integrated workflow connecting functional models, component variability, sizing and mission simulation. • Integrated ADORE modelling, model transformations, OpenMDAO sizing and reinforcement-learning-based architecture exploration, in collaboration with DLR. • Developed a Python mission simulator covering payload acquisition, onboard processing, communications, power, battery and thermal dynamics. • Evaluated 3,500 configurations across three simulation durations for performance prediction; contributed to a toolchain identifying Pareto-optimal designs. Technologies: C, C++20, Python, ADORE, OpenMDAO, model transformations, automated testing and CI.

Cross-functional R&D spanning automotive embedded graphics, software architecture and model-based engineering toolchains, alongside an industrial PhD. CONTEXT Automotive cockpit development required both efficient graphics software for resource-constrained hardware and methods to compare hardware/software architectures against performance, feasibility and cost requirements. CONTRIBUTIONS • Contributed to a C/C++ graphics toolchain combining a scene compiler and a lightweight embedded rendering engine, moving scene-specific processing from runtime to code generation. • Worked across software architecture, generated code and low-level graphics execution to address platform constraints and performance requirements. • Developed model-based architecture exploration capabilities combining application and hardware variability, software-to-hardware allocation, executable models and automated verification. • Connected embedded implementation constraints with architecture evaluation to support engineering trade-offs and early feasibility studies. This work brought together two complementary perspectives: developing the embedded product and improving the tools and methods used to design it. Technologies and methods: C, C++, Java, OpenGL ES, embedded graphics, code generation, hardware/software co-design and model-based systems engineering.

Developed embedded graphics software and code-generation tools for automotive instrument clusters within Visteon R&D. CONTEXT Deliver real-time 3D graphics on the first automotive 3D microcontroller running at 240 MHz with 256 KB RAM, requiring a lightweight alternative to existing commercial graphics frameworks. CONTRIBUTIONS • Designed and developed a C++11 scene compiler translating XML scene descriptions into optimised, scene-specific C/OpenGL ES 1.1 code, shifting processing from runtime to build time. • Developed a lightweight C rendering runtime for FreeRTOS and bare-metal environments. • Optimised 3D models, graphics buffers, vendor OpenGL ES driver code and DMA calls to meet platform constraints. • Worked across toolchain architecture, code generation and low-level execution to make the graphics solution viable on the target hardware. RESULT Delivered the first real-time 3D instrument-cluster implementation on this platform, demonstrated at CES 2016. Technologies: C, C++11, XML, OpenGL ES 1.1, ARM Cortex-R5, FreeRTOS, bare-metal development and DMA engines.

Explored the feasibility of software-based graphics rendering on an ARM Cortex-A5 platform without a GPU for automotive embedded applications. CONTRIBUTIONS • Profiled a C rendering pipeline and evaluated compiler configurations to identify performance bottlenecks. • Optimised vertex transformation and projection routines in ARM/NEON assembly, using SIMD, instruction-level parallelism and cache-aware optimisation. • Benchmarked the optimised routines against C code compiled with Green Hills at -O3 with vectorisation enabled. RESULTS Achieved 10% faster execution for the targeted routines compared with the compiler-optimised C baseline. Compiler configurations identified during this work were reused in other projects. Technologies: C, ARM assembly, NEON SIMD, software rendering, performance profiling and Green Hills toolchain.