SIMOND PIERRE DIOP

Physical layout implementation of components for the creation of photolithography masks, covering a wide range of technology nodes and advanced R&D projects. Physical verification of layouts using design rule checks (DRC), including the coding of custom rules to ensure compliance with technological constraints. Final mask assembly while ensuring adherence to process constraints (e.g., density, alignment). Mask Data Preparation (MDP) for manufacturing, in close collaboration with foundry partners and mask vendors. Proficient in EDA tools for mask design, such as Cadence, Siemens, and Synopsys. Tools: Cadence, linux, Calibre, Cats Masks Equipment: 1X Mask (4P,5P,7P,9P), and Reticles (200mm, 300mm)

Objective: Reduction of the operating current of a voltage and current reference cell based on a Bandgap circuit in a USB PD CC IO. Assignments: Bibliographical research, design, layout and simulation of the Bandgap circuit in 18nm technology for the complete IP. Tools: Cadence / Virtuoso environment Eldo/Spectre simulator Knowledge: Mastering the Bandgap, Startup, Trimming Schmitt Trigger and beta Multiplier circuits, reading and writing a Netlist, Layout, Verilog A

Assignments: Realization of a glare study for a photovoltaic plant installation authorization. Tools: Matlab, Google Earth